int iLength;
pdwFlashAddr = (DWORD*)FLASH_START_ADDRESS;
iLength = g_dwSaveCount;
dwBlockCounter = 0;
while (1)
{
pdwBufAddr = (DWORD*)(g_dwDramBase[dwBlockCounter++]);
for (dwInBlockCounter=0;
dwInBlockCounter<((DWORD)DRAM_BLOCK_SIZE/4);
dwInBlockCounter++)
{
dwValue = *pdwBufAddr++;
*((UCHAR*)pdwFlashAddr) = FLASH_COMMAND_WRITE;
*pdwFlashAddr = ((FLASH_COMMAND_STATUS<<16) |
(dwValue&0x0000FFFF));
while (!(*pdwFlashAddr & FLASH_STATUS_READY));
*pdwFlashAddr = (dwValue&0xFFFF0000) | FLASH_COMMAND_WRITE;
*((UCHAR*)pdwFlashAddr) = FLASH_COMMAND_STATUS;
while (!(*pdwFlashAddr & FLASH_STATUS_READY));
pdwFlashAddr++;
if ((iLength-=4) <= 0)
{
*((UCHAR*)FLASH_START_ADDRESS) =
(UCHAR)FLASH_COMMAND_READ;
/*
dwCheckSum = 0;
pdwFlashAddr = (DWORD*)FLASH_START_ADDRESS;
for (iLength=(int)g_dwSaveCount; iLength!=0; iLength--)
{
dwCheckSum += *((UCHAR*)pdwFlashAddr);
(UCHAR*)pdwFlashAddr++;
}
if (dwCheckSum != g_dwCheckSum)
PrintMsg((UCHAR*)g_szProgramFlashError);
*/
return;
}
}
}
}
void FlashErrorHandler(UCHAR * pszMsg, UCHAR * pcAddr2Dump)
{
register DWORD dw, dw1;
*((UCHAR*)FLASH_START_ADDRESS) =(UCHAR)FLASH_COMMAND_READ;
PrintMsg(pszMsg);
PrintDword((DWORD)pcAddr2Dump);
for (dw=0; dw<16; dw++)
{
for (dw1=0; dw1<16; dw1++)
{
ToAscii(*pcAddr2Dump++, (UCHAR*)&g_szByteMsg + 2);
PrintMsg((UCHAR*)&g_szByteMsg);
}
PrintMsg("\r\n");
}
Beep();
PrintMsg((UCHAR*)&g_szBootLdrEnd);
while(1);
}
/**** end ****/
/*************************************************************
void SetCp15(DWORD uCp15Val)
{
asm ("mcr p15, 0, %0, c1, c0, 0;" : : "r"(uCp15Val) );
}
DWORD ReadCp15()
{
register DWORD x;
asm ("mrc p15, 0, %0, c1, c0, 0;" : "=r"(x) : );
return x;
}
**************************************************************/
/* *************************************************************
clps7111.h
Cirrus CLPS7111 (ARM710A core) CPU registers defination
**************************************************************/
#ifndef __CLPS7111_H__
#define __CLPS7111_H__
#define HW1base 0x80000000
//ports A-D all 8 bits wide
#define HW1_PADR 0x00 // Port A data register
#define HW1_PBDR 0x01 // Port B data register
#define HW1_PDDR 0x03 // Port D data register
#define HW1_PADDR 0x40 // Port A data direction register
#define HW1_PBDDR 0x41 // Port B data direction register
#define HW1_PDDDR 0x43 // Port D data direction register
//port E 3 bits wide
#define HW1_PEDR 0x80 // Port E data register
#define HW1_PEDDR 0xc0 // Port E data direction register
#define HW1_SYSCON1 0x100 // System control register [32]
#define HW1_SYSFLG1 0x140 // System status flags [RO,32]
#define HW1_MEMCFG1 0x180 // Exp/ROM mem cfg register 1 [32]
#define HW1_MEMCFG2 0x1c0 // Exp/ROM mem cfg register 2 [32]
#define HW1_DRFPR 0x200 // DRAM refresh period reg. [8]
#define HW1_INTSR1 0x240 // Interrupt status register [RO,16]
#define HW1_INTMR1 0x280 // Interrupt mask register [16]
#define HW1_LCDCON 0x2c0 // LCD control register [32]
#define HW1_TC1D 0x300 // data to/from TC1 [16]
#define HW1_TC2D 0x340 // data to/from TC2 [16]
#define HW1_RTCDR 0x380 // real time clock data reg. [32]
#define HW1_RTCMR 0x3c0 // real time clock match reg. [32]
#define HW1_PMPCON 0x400 // DC to DC pump control reg. [12]
#define HW1_CODR 0x440 // CODEC data I/O reg. [8]
#define HW1_UARTDR1 0x480 // UART1 FIFO data register [8]
#define HW1_UBRLCR1 0x4c0 // UART1 bit rate and line ctrl reg. [32]
#define HW1_SYNCIO 0x500 // SSI data reg. for master only [16]
#define HW1_PALLSW 0x540 // LSW of LCD palette register [32]
#define HW1_PALMSW 0x580 // MSW of LCD palette register [32]
#define HW1_STFCLR 0x5c0 // clear startup reason flags [WO,-]
#define HW1_BLEOI 0x600 // clear batt. low interrupt [WO,-]
#define HW1_MCEOI 0x640 // clear media change interrupt [WO,-]
#define HW1_TEOI 0x680 // clear tick/watchdog interrupt [WO, -]
#define HW1_TC1EOI 0x6c0 // clear TC1 interrupt [WO,-]
#define HW1_TC2EOI 0x700 // clear TC2 interrupt [WO,-]
#define HW1_RTCEOI 0x740 // clear RTC match interrupt [WO,-]
#define HW1_UMSEOI 0x780 // clear UART modem stat changed [WO,-]
#define HW1_COEOI 0x7c0 // clear CODEC sound interrupt [WO,-]
#define HW1_HALT 0x800 // enter idle state [WO,-]
#define HW1_STDBY 0x840 // enter standby state [WO,-]
#define HW2base (HW1base|0x1000)
#define HW2_FRBADDR 0x000 // LCD frame buffer start address [24]
#define HW2_SYSCON2 0x100 // System control register 2
#define HW2_SYSFLG2 0x140 // System status register 2
#define HW2_INTSR2 0x240 // Interrupt status register [RO]
#define HW2_INTMR2 0x280 // Interrupt mask register
#define HW2_UARTDR2 0x480 // UART2 data register [8/11]
#define HW2_UBRLCR2 0x4c0 // UART2 control register [32]
#define HW2_SRXEOF 0x600 // Write to clear Rx FIFO overflow flag
#define HW2_KBDEOI 0x700 // Write to clear keyboard interrupt [WO,-]
//these registers have the same offset in each bank and share some bitfields
//it's useful to give them a generic name.
#define HW_SYSCON HW1_SYSCON1
#define HW_SYSFLG HW1_SYSFLG1
#define HW_UBRLCR HW1_UBRLCR1
#define HW_UARTDR HW1_UARTDR1
//SYSCON1/SYSCON2 bitfield
//bits 0-3: keyboard scan
#define SYSCON1_KBS_MASK 15
#define SYSCON1_KBS_ALLHIGH 0
#define SYSCON1_KBS_ALLLOW 1
#define SYSCON1_KBS_ALLHIZ 2
#define SYSCON1_KBS_COL0 8
#define SYSCON1_KBS_COL1 9
#define SYSCON1_KBS_COL2 10
#define SYSCON1_KBS_COL3 11
#define SYSCON1_KBS_COL4 12
#define SYSCON1_KBS_COL5 13
#define SYSCON1_KBS_COL6 14
#define SYSCON1_KBS_COL7 15
#define SYSCON1_TC1M (1<<4) // TC1 mode (set=prescale)
#define SYSCON1_TC1S (1<<5) // TC1 source (set=512KHz)
#define SYSCON1_TC2M (1<<6) // TC2 mode
#define SYSCON1_TC2S (1<<7) // TC2 source
#define SYSCON1_UART1EN (1<<8) // enable UART1
#define SYSCON1_BZTOG (1<<9) // drive buzzer directly
#define SYSCON1_BZMOD (1<<10) // 0: buzzer uses BZTOG
#define SYSCON1_DBGEN (1<<11) // debug mode
#define SYSCON1_LCDEN (1<<12) // enable LCD controller
#define SYSCON1_CDENTX (1<<13) // CODEC i/f enable Tx
#define SYSCON1_CDENRX (1<<14) // CODEC i/f enable Rx
#define SYSCON1_SIREN (1<<15) // HP SIR encoding enable
#define SYSCON1_ADCKSEL_MASK (3<<16) // ADC clock select
#define SYSCON1_ADCKSEL_SHIFT 16
#define SYSCON1_EXCKEN (1<<18) // external expansion clock enable
#define SYSCON1_WAKEDIS (1<<19) // disable wakeup switchon
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