#define SYSCON1_IRTXM (1<<20) // IrDA Tx mode strategy
//SYSCON2
//bit 0: serial interface select
#define SYSCON2_SERSEL 1
#define SYSCON2_CODEC 1 // CODEC Enable
#define SYSCON2_KBD6 (1<<1) // if high only pins 0 to 5 of pA are kbd
#define SYSCON2_DRAMWID (1<<2) // 1=16-bit DRAM, 0-32-bit DRAM
#define SYSCON2_KBWDIS (1<<3) // enforce IRQ mask register for
wakeup
#define SYSCON2_PCMCIA1 (1<<5) // enable PCMCIA interface 1 (cs4)
#define SYSCON2_PCMCIA2 (1<<6) // enable PCMCIA interface 2 (cs5)
#define SYSCON2_UART2EN (1<<8) // enable UART2
#define SYSCON2_OSTB (1<<12) // twiddle clocks somehow
#define SYSCON2_CLKENSL (1<<13) // high/low: output run/clken on run/clken pin
//SYSFLG/SYSFLG2 bitfield
#define SYSFLG1_MCDR (1<<0) // media changed direct read
#define SYSFLG1_DCDET (1<<1) // 1: mains power
#define SYSFLG1_WUDR (1<<2) // wakeup direct read
#define SYSFLG1_WUON (1<<3) // started by wakeup
//bits 4-7: display ID nibble
#define SYSFLG1_DID_mask (15<<4)
#define SYSFLG1_CTS (1<<8) // UART1 CTS
#define SYSFLG1_DSR (1<<9) // UART1 DSR
#define SYSFLG1_DCD (1<<10) // UART1 DCD
#define SYSFLG1_UBUSY1 (1<<11) // UART1 busy
#define SYSFLG1_NBFLG (1<<12) // new battery (clear w/ STFCLR)
#define SYSFLG1_RSTFLG (1<<13) // reset pressed (clear w/ STFCLR)
#define SYSFLG1_PFFLG (1<<14) // power fail (clear w/ STFCLR)
#define SYSFLG1_CLDFLG (1<<15) // power on reset (clear w/ STFCLR)
//bits 16-21: number of 64Hz ticks since last RTC increment
#define SYSFLG1_RTCDIV_mask (63<<16)
#define SYSFLG1_URXFE1 (1<<22) // UART rx FIFO empty
#define SYSFLG1_UTXFF1 (1<<23) // UART tx FIFO full
#define SYSFLG1_CRXFE (1<<24) // CODEC rx FIFO empty
#define SYSFLG1_CTXFF (1<<25) // CODEC tx FIFO full
#define SYSFLG1_SSIBUSY (1<<26) // 1: SSI is shifting data
//0: data clear to read
#define SYSFLG1_BOOTBIT0 (1<<27)
#define SYSFLG1_BOOTBIT1 (1<<28)
// bootbit0 bootbit1 boot option
// 0 0 32-bit
// 0 1 8-bit
// 1 0 16-bit
// 1 1 reserved
#define SYSFLG1_RESERVED (1<<29)
//bits 30-31: version ID
#define SYSFLG1_VERID_mask (3<<30)
#define SYSFLG2_CHKMODE (1<<6) // 18/13 mode flag
#define SYSFLG2_UBUSY2 (1<<11) // UART2 busy
#define SYSFLG2_URXFE2 (1<<22) // UART2 rx FIFO empty
#define SYSFLG2_UTXFF2 (1<<23) // UART2 tx FIFO full
// ;; MEMCFG1
// ;; Expansion and ROM selects
// ;; byte0 : Ncs0
// ;; byte1 : Ncs1
// ;; byte2 : Ncs2
// ;; byte3 : Ncs3
// ;; MEMCFG2
// ;; Expansion and ROM selects
// ;; byte0 : cs4
// ;; byte1 : cs5
// ;; byte2 : RESERVED (local SRAM)
// ;; byte3 : Boot ROM (cs7)
// ;; chip select bytes (cs7, cs4-5 in non-PCMCIA mode, Ncs0-3)
// ;; b0-1: bus width
// ;; maps onto expansion transfer mode according to value here
// ;; and BOOTBIT{0,1} (=BOOTWID[1:0])
// ;; b2-3: random access wait state
// ;; value #states (nS) speed
// ;; 0 4 250
// ;; 1 3 200
// ;; 2 2 150
// ;; 3 1 100
// ;; b4-5: sequential access wait state
// ;; value #states (nS) speed
// ;; 0 3 150
// ;; 1 2 120
// ;; 2 1 80
// ;; 3 0 40
// ;; b6: SQAEN
// ;; b7: CLKENB
#define MEMCFG_WIDTH32 (0<<0)
#define MEMCFG_WIDTH16 (1<<0)
#define MEMCFG_WIDTH8 (2<<0)
#define MEMCFG_WIDTHRESERVED (3<<0)
#define MEMCFG_RA_1WAIT (3<<2)
#define MEMCFG_RA_2WAITS (2<<2)
#define MEMCFG_RA_3WAITS (1<<2)
#define MEMCFG_RA_4WAITS (0<<2)
#define MEMCFG_SA_0WAITS (3<<4)
#define MEMCFG_SA_1WAIT (2<<4)
#define MEMCFG_SA_2WAITS (1<<4)
#define MEMCFG_SA_3WAITS (0<<4)
#define MEMCFG_SQAEN (1<<6)
#define MEMCFG_CLKENB (1<<7)
//DRAM refresh period register
#define DRFPR_RFSHEN (1<<7)
#define DRFPR_RFDIV_MASK 127
//interrupt bits for INTSR[12] and INTMR[12]
#define INT1_EXTFIQ (1<<0) // external FIQ
#define INT1_BLINT (1<<1) // battery low FIQ
#define INT1_WEINT (1<<2) // watchdog expired FIQ
#define INT1_MCINT (1<<3) // media changed FIQ
#define INT1_CSINT (1<<4) // CODEC sound
#define INT1_EINT1 (1<<5) // external IRQ 1
#define INT1_EINT2 (1<<6) // external IRQ 2
#define INT1_EINT3 (1<<7) // external IRQ 3
#define INT1_TC1OI (1<<8) // TC1 underflow
#define INT1_TC2OI (1<<9) // TC2 underflow
#define INT1_RTCMI (1<<10) // RTC compare match
#define INT1_TINT (1<<11) // 64Hz tick
#define INT1_UTXINT1 (1<<12) // UART1 tx FIFO half empty
// or no data in Tx hold. reg.
#define INT1_URXINT1 (1<<13) // UART1 rx FIFO half full
// or valid data in Rx hold. reg.
#define INT1_UMSINT (1<<14) // UART1 modem status changed
#define INT1_SSEOTI (1<<15) // SSI end of transfer
#define INT2_KBDINT (1<<0) // keyboard interrupt
#define INT2_UTXINT2 (1<<12) // UART2 tx FIFO half empty
#define INT2_URXINT2 (1<<13) // UART2 rx FIFO half full
//PSR bits
#define PSR_I (1<<7) // IRQ disable bit
#define PSR_F (1<<6) // IRQ disable bit
#define PSR_LOCK (PSR_I+PSR_F)
#define PSR_MODEMASK 0x1f // Mode mask
#define PSR_MODEUSER 0x10
#define PSR_MODEFIQ 0x11
#define PSR_MODEIRQ 0x12
#define PSR_MODESVC 0x13
#define PSR_MODEABORT 0x17
#define PSR_MODEUNDEF 0x1b
#endif /*#ifndef __CLPS7111_H__*/
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